A Novel Approach to Design of 6T (8 X 8) SRAM Cell Low Power Dissipation Using MCML Technique on 45 Nm
نویسندگان
چکیده
The most research on the power consumption of 6T SRAM has been focused on the static power dissipation and the power dissipated by the leakage current. On the other hand, as the current VLSI technology scaled down, the sub-threshold current increases which further increases the power consumption. In this paper we have proposed 6T (8 X 8) SRAM cells using MCML technology which will reduce the leakage power in SRAM cell and will control the sub-threshold current. The results of 6T (8 X 8) SRAM cell array using MCML technology in 45 nm library on Cadence Virtuoso Tool, represents that there is a significant reduction in power dissipation and leakage current using MCML technology.
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